module dat_gen(i_loaddr, i_rd, o_dat);

input      [ 1:0] i_loaddr;
input      [31:0] i_rd;
output reg [31:0] o_dat;

always @* begin
  case (i_loaddr)
    2'b00: o_dat =  i_rd;
    2'b01: o_dat = {i_rd[23:0], i_rd[31:24]};
    2'b10: o_dat = {i_rd[15:0], i_rd[31:16]};
    2'b11: o_dat = {i_rd[ 7:0], i_rd[31: 8]};
  endcase
end

endmodule
